Research in High Performance Computing

I am a Pre-Doctoral researcher in the TU Wien at the Research Group Parallel Computing. My research interests revolve around the High Performance Computing (HPC) area. Specifically, performance optimization of HPC applications and the performance of MPI libraries such as Open MPI and MPICH. Past research includes topics on Interconnects, Resilience and Fault-tolerance.

My current research thesis is concerned with the mapping and colocation of parallel applications to the deep resource hierarchy of HPC systems. To delve deeper into this subject I developed a new profiling tool called mpisee for the MPI to explore the use and mapping of MPI communicators by the applications.


  1. Ioannis Vardas, Sascha Hunold, Jordy I. Ajanohoun and Jesper Larsson Träff: mpisee: MPI Profiling for Communication and Communicator Structure, presented at the HIPS Workshop of IPDPS 2022
  2. Ioannis Vardas, Manolis Ploumidis and Manolis Marazakis: Exploring the impact of node failures on the resource allocation for parallel jobs, 14th Workshop on Resiliency in High Performance Computing (Resilience) in Clusters, Clouds, and Grids
  3. Ioannis Vardas, Manolis Ploumidis and Manolis Marazakis: Towards Communication Profile, Topology and Node Failure Aware Process Placement, 2020 IEEE 32nd International Symposium on Computer Architecture and High Performance Computing
  4. Jesper Larsson Träff, Ioannis Vardas: Library Development with MPI: Attributes, Request Objects, Group Communicator Creation, Local Reductions, and Datatypes, EuroMPI '23: Proceedings of the 30th European MPI Users' Group Meeting
  5. Hunold, Sascha and Ajanohoun, Jordy I. and Vardas, Ioannis and Träff, Jesper Larsson: An Overhead Analysis of MPI Profiling and Tracing Tools, PERMAVOST '22: Workshop on Performance EngineeRing, Modelling, Analysis, and VisualizatiOn Strategy
  6. Dimitris Giannopoulos, Nikos Chrysos, Evangelos Mageiropoulos, Giannis Vardas, Leandros Tzanakis, Manolis Katevenis: Accurate Congestion Control for RDMA Transfers, 2018 IEEE/ACM International Symposium on Networks-on-Chip (NOCS)


Side projects

  • YAC_SIM a cache memory simulator for a simple one-level cache memory scheme running in command line
  • Implementation of RISC-V standard in System Verilog RV32IC

Other interests


  • Computer Architecture and Parallel Computer Architecture
  • RISC-V Open Instruction Set Architecture
  • Linux Kernel and GNU/Linux operating system

Development tools

  • Emacs and Org mode